Differential power analysis (DPA) side-channel attacks pose serious threats for embedded system security and crypto-hardware systems. DPA attacks statistically find the correlation between power consumption and secret data in crypto-hardware.
A number of transistor through register-transfer level countermeasures have been proposed with varying DPA attack resistivity. DPA attack defense techniques include randomization techniques and masking countermeasures, sense amplifier based logic (SABL), and wave dynamic differential logic (WDDL).
Randomization techniques and masking countermeasures conceal intermediate variables and agitate power information. These countermeasures make it difficult to perform DPA but do not guarantee to obscure the power information. Randomization techniques and masking countermeasures also suffer from performance degradation.
Sense Amplifier Based Logic (SABL) and other transistor level countermeasures can minimize the power imbalance in a circuit. SABL is prohibitively expensive and time-consuming to design a full-custom chip every time.
Wave dynamic differential logic (WDDL), a dual-rail pre-charge logic standard cell countermeasure, guarantees a 100% switching factor by placing a complementary cell next to every original cell. For example, AND cells are paired with OR cells. Every WDDL cell is comprised of 2 standard cells and switches, including at least one of the primary and complementary cells. As a result, WDDL incurs over 2× area and energy overheads due to pairing the complementary cell with every cell in the original circuit. WDDL results in more than a 100% increase in energy consumption and WDDL fails in suppressing differential power. WDDL is still vulnerable to DPA attacks, and DPA attacks on WDDL still leak secret keys to adversaries.